Document Details

Document Type : Thesis 
Document Title :
FPGA-based Hardware Accelerator for SoftMax Function 2021
مسرع الأجهزة المستند إلى مجموعة بوابة قابلة للبرمجة الميدانية لوظيفة دالة السوفت ماكس
 
Subject : Faculty of Engineering 
Document Language : Arabic 
Abstract : Softmax function is an integral part of object detection frameworks based on all deep or shallow neural networks. While the configuration of different operation layers in a neural network can be quite different, softmax operation is fixed. With the recent advances in object detection approaches, especially with the introduction of highly accurate convolutional neural networks, researchers and developers have suggested different hardware architectures to speed up the overall operation of these compute-intensive algorithms. Xilinx, one of the leading FPGA vendors, has recently introduced a deep neural network development kit for exactly this purpose. However, due to the complex nature of softmax arithmetic hardware involving exponential function, this functionality is only available for bigger devices. For smaller devices, this operation is bound to be implemented in software. In this thesis, we will explore the hardware implementation of this function in the light of the earlier works reported in the literature. The main objective of this study will be to come up with an efficient and low-cost implementation that is suitable for smaller devices as well. For this purpose, we intend to look into approximate and piece-wise linear implementations as well. The final product will be implemented as a hardware accelerator with industry standard bus interface so that it can be integrated seamlessly with Xilinx processor and programmable logic. One other matter of concern is the design, development and testing of full hardware systems which requires a lot of effort and time. Thus, there is an increasing trend of describing the circuit behavior using high-level synthesis tools to reduce the development time and spend more effort at the algorithmic design level. Hardware Description Language (HDL) Coder and Vision HDL toolboxes in Simulink® by Mathworks® provide higher level abstraction of image processing and machine learning algorithms for quick deployment on a variety of target hardware. Resultantly, the development cycle of multimedia processing hardware applications using these tools gets shortened. Thus, in this spirit, the project will be implemented using high-level synthesis tools available in Matlab environment. The test setup will use standard neural networks such as Resnet and Squeezenet etc. to determine the functional accuracy. The entire setup will be ported to a Xilinx FPGA development board i.e. Zedboard which contains the necessary hardware components such as USB, Ethernet and HDMI interfaces etc. to implement a fully working system capable of processing a machine learning application in real-time. 
Supervisor : Dr. Mohammed Belal 
Thesis Type : Master Thesis 
Publishing Year : 1444 AH
2022 AD 
Added Date : Tuesday, February 28, 2023 

Researchers

Researcher Name (Arabic)Researcher Name (English)Researcher TypeDr GradeEmail
محمد عبدالله الشهرانيAlshahrani, Mohammed AbdullahResearcherMaster 

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 49068.pdf pdf 

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